I. Field of the Invention
The present invention relates to signal amplifiers. More specifically, the present invention relates to a circuit and method for highly-efficient signal amplification over a wide dynamic range wherein the output level and intercept point are determined from the input level and modulation type of the input signal.
II. Description of the Related Art
In the field of wireless telecommunications, such as in various cellular, Personal Communication Services (PCS), and Wireless Local Loop (WLL) communication systems, many different communication standards exist. For example, Code-Division Multiple Access (CDMA) digital communications may be governed by either Telecommunications Industry Association (TIA)/Electronics Industries Association (EIA) Interim Standard IS-95 (series) for cellular systems, or by ANSI J-STD-008 for PCS systems. Additionally, Time-Division Multiple Access (TDMA) digital communications may be governed by the TIA/EIA IS-54, or by the European standard Global System for Mobile Communications (GSM). Furthermore, analog FM-based communications systems may be governed by the Advanced Mobile Phone System (AMPS) standard, or a related standard such as N-AMPS. Other wireless communication standards also exist for both digital and analog modulation.
For each of these communication system standards, a long-felt need exists for an amplifier for a wireless communication device which exhibits the high linearity needed for signal integrity, as well as the high efficiency needed for longer operating time. This is particularly true for dual-mode communication devices that can operate according to two different standards (such as CDMA/AMPS), because each of the standards may have different linearity requirements. For example, the linearity requirements in a CDMA communication device are more stringent than those of an AMPS communication device. Thus, a dual-mode digital/analog communication device would benefit greatly from being able to take advantage of a high linearity amplifier while operating in a digital mode where there may be strict linearity requirements, while still being able to operate with high efficiency while in an analog mode where the linearity requirements are more relaxed.
However, as is known in the art of amplifier design, high linearity and high efficiency are generally mutually exclusive design considerations. That is to say, when one is designing a particular transistor-based amplifier, one must usually make a trade-off between high linearity and high efficiency. The difference between high linearity and high efficiency is manifested by saturation characteristics which are determined by the load impedance in relation to the current capability and the breakdown voltage of the amplifier. In turn, the load impedance, current capability and breakdown voltage of the amplifier are a function of the amplifier device type, construction, periphery (e.g., gate area), and supply voltage. Thus, a designer who wishes to design a highly linear amplifier will generally choose a relatively low load impedance for a given supply voltage. Highly linear amplifiers maintain the integrity of the input signal envelope at the expense of higher average power dissipation. This high average power dissipation which results from overlap of current and voltage in the transistor over time is particularly undesirable in a battery-powered portable transmitter because it reduces battery life, and thus the transmit time, of the portable transmitter between battery charges.
Conversely, a designer who wishes to design a highly efficient amplifier will generally choose a relatively higher load impedance for the same supply voltage. Highly efficient amplifiers maintain a lower average power dissipation at the expense of xe2x80x9cclippingxe2x80x9d of the input signal at high input amplitudes due to premature saturation of the amplifier. Although clipping the input signal gives rise to high efficiency and longer battery life because the device""s power dissipation is minimized during saturation, it results in distortion of the input signal envelope, and consequent generation of in-band spectral sidelobes. Furthermore, clipping generates higher-order harmonics that may be spread outside of the allowed operating bandwidth of the transmitter, causing interference to other RF devices transmitting or receiving on other frequencies.
Although there have been various attempts to create a highly efficient amplifier that is also highly linear, these attempts contain inherent problems which limit their effectiveness. For example, Doherty-type amplifiers are well known in the art as being highly efficient and also highly linear. A Doherty-type amplifier modulates the load impedance in response to the envelope of the input signal. In a Doherty-type amplifier, two amplifiers are connected in parallel, with the output of one of the amplifiers in series with a quarter-wavelength phase shifter. An example of such an amplifier is illustrated in U.S. Pat. No. 5,568,086 to Schuss et al, entitled xe2x80x9cLINEAR POWER AMPLIFIER FOR HIGH EFFICIENCY MULTI-CARRIER PERFORMANCE.xe2x80x9d However, a significant drawback to the Doherty-type design of Schuss et al is that a quarter-wavelength phase shifter may be difficult and costly to realize at certain frequencies. Additionally, Doherty-type amplifiers are narrowband xe2x80x9ctunedxe2x80x9d amplifiers that operate best around a single frequency and are ill-suited for use in a broadband application such as digital wireless telephony.
Another example of a highly efficient amplifier is illustrated in U.S. Pat. No. 5,175,871 to Kunkel, entitled xe2x80x9cPOWER AMPLIFIER FOR A CELLULAR TELEPHONE.xe2x80x9d The amplifier of Kunkel uses a non-linear amplifier stage in conjunction with a separate linear amplifier stage. A switch is used to select the non-linear amplifier stage when non-linear behavior is desired, and to select the linear amplifier stage when linear behavior is desired. However, a significant drawback of Kunkel is the increased expense of providing two separate amplifiers, each with its own design characteristics.
In U.S. Pat. No. 5,661,434, entitled xe2x80x9cHIGH EFFICIENCY MULTIPLE POWER LEVEL AMPLIFIER CIRCUIT,xe2x80x9d issued Aug. 26, 1997 to Brozovich et al, a high efficiency power amplifier is disclosed. The high efficiency power amplifier of Brozovich comprises a plurality of power amplifier stages coupled in a cascade configuration. At least one of the amplification stages includes a signal switching network for switching among one or any combination of the power amplifiers. A signal switch control circuit, external to the amplifier circuit, controls the switches. A drawback of this design is that the signal switch control circuit provides external control to the switches. By using external control to the switches, the complexity of hardware and software is increased.
Thus, there is a resultant need for an amplifier that is both highly efficient and highly linear which avoids the drawbacks inherent in other designs.
The present invention is a novel and improved circuit and method for amplifying an input signal. Broadly described, the circuit comprises an amplifier circuit having an input for receiving the input signal, and an amplifier control circuit, coupled to the amplifier circuit, for varying a supply power and a device periphery of the amplifier circuit in response to an amplitude envelope of the input signal. In this manner, the amplifier control circuit can control the linearity and the efficiency of the amplifier circuit using the characteristics of the input signal itself, without relying on any external processing.
An exemplary embodiment of the amplifier control circuit comprises an envelope detector that detects the input signal amplitude envelope, and that generates an envelope detection signal in response thereto. At least one threshold detector, coupled to the envelope detector, compares the envelope detection signal to a threshold, and generates a threshold comparison signal in response thereto. An amplitude-modulation (AM) detector, coupled to the envelope detector, detects whether there is amplitude modulation present on the input signal, and generates a mode detection signal in response thereto. At least one power regulator, coupled to the at least one threshold detector and the AM detector, varies the supply power in response to the threshold comparison signal and the mode detection signal.
An exemplary embodiment of the amplifier circuit of the present invention comprises a first amplifier stage and a second amplifier stage. The amplifier control circuit varies the device periphery of the amplifier circuit by independently enabling and disabling the first amplifier stage and the second amplifier stage.
In a first embodiment, the first and second amplifier stages are coupled in a cascade configuration. In this cascade configuration, the amplifier circuit may further comprise a first bypass switch, coupled to the first amplifier stage and the second amplifier stage and interposed therebetween, for bypassing the second amplifier stage in response to the threshold comparison signal and the mode detection signal, thereby disabling the second amplifier stage. Optionally, the cascade-configured amplifier circuit may further comprise an output matching network, coupled to an output of the amplifier circuit, and a second bypass switch, coupled to the first bypass switch and the output matching network and interposed therebetween. This additional shunt switch may be used to provide additional isolation when the amplifier circuit is operating in a high power mode.
In a separate cascade-configured embodiment, the second amplifier stage may comprise a feedthrough amplifier which includes an amplifier and a feedback network, coupled in parallel with the amplifier, such that signals incident at an input of the amplifier are conducted through the feedback network to an output of amplifier.
In another embodiment, the first and second amplifier stages are coupled in a parallel configuration. In the amplifier control circuit of this parallel configuration, a DC bias control circuit, coupled to the AM detector and the at least one threshold detector, selectively applies a DC bias voltage to an input of the first amplifier stage and to an input of the second amplifier stage in response to the threshold comparison signal and the mode detection signal. The DC bias control circuit thereby enables and disables individual ones of the parallel-configured stages.
The present invention also includes a method for amplifying an input signal in an circuit having an amplifier circuit controlled by an amplifier control circuit. The method, defined broadly, comprises the steps of detecting an amplitude envelope of the input signal, comparing the input signal amplitude envelope to a threshold, varying a device periphery of the amplifier circuit in response to the comparing step, determining a presence of amplitude-modulation (AM) in the input signal amplitude envelope, and varying a power supply to the amplifier circuit in response to the determining step. In this manner, the present invention uses the characteristics of the input signal to control the linearity and efficiency of the amplifier circuit.
Specifically, the method of the present invention varies the amplifier device periphery by increasing the device periphery if the input signal amplitude envelope is greater than or equal to the threshold, and by decreasing the device periphery if the input signal amplitude envelope is less than the threshold. Additionally, the method of the present invention varies the power supply to the amplifier circuit by increasing the power supply if AM is present in the input signal amplitude envelope, and by decreasing the power supply if AM is not present in the input signal amplitude envelope.
In an embodiment wherein the amplifier circuit comprises first and second amplifier stages, the method of the present invention varies the device periphery by independently enabling and disabling the first and second amplifier stages. In an embodiment wherein the first and second amplifier stages are coupled in a cascade configuration, the method of the present invention varies the device periphery by bypassing said second amplifier stage.
In an embodiment wherein the first and second amplifier stages are coupled in a parallel configuration, the method of the present invention varies the device periphery by selectively applying a DC bias voltage to an input of the first amplifier stage and an input of the second amplifier stage.